1. Field of the Invention
In general, the present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to enhancement of an operating current of a super-miniaturized MIS semiconductor device and super enhancement of an operating speed of the MIS semiconductor device.
2. Description of the Related Art
Enhancement of performance of an insulated-gate field-effect transistor or, in particular, a MIS field-effect transistor (hereinafter, simply abbreviated to MISFET) employed in a super-density semiconductor device is based on a scaling law and has been successful. The success of the enhancement of an insulated-gate field-effect transistor's performance is attributed to a decrease in applied power-supply voltage, a decrease in transistor area and miniaturization of gate dimensions. The decrease in transistor area and the miniaturization of gate dimensions should provide a merit of a decrease in parasitic capacitance.
If the gate dimensions are decreased, however, a short-channel effect is resulted in, causing a threshold voltage to fluctuate. In order to reduce the short-channel effect accompanying miniaturization of the length of the gate electrode in the super miniaturized MIS described above, an effort to make a junction of a source diffusion layer and a drain diffusion layer shallow is promoted.
Even in the case of a MISFET with a shallow junction of the source diffusion layer and the drain diffusion layer, as the device is miniaturized to reach a gate length equal to or smaller than 100 nm, it becomes difficult to assure a large effective channel length because of the existence of an overlap area between the gate and the source/drain diffusion layers and, hence, hard to suppress the short-channel effect This overlap area is generated due to diffusion of impurities during a heat treatment carried out for the purpose of activating the impurities.
In order to solve the problems described above, in accordance with a typical solution disclosed in Japanese Patent Laid-open No. H7(1995)-245391, after a first side-wall spacer is provided on a side wall of the gate electrode, impurities are introduced with the gate electrode and the first side-wall spacer used as masks to form an N- or P-source diffusion layer area and a drain diffusion layer area. As a result, it is possible to form an effective structure in which a large effective gate length is assured.
In addition, in accordance with a disclosure described in Japanese Patent Laid-open No. H5(1993)-3206 as a typical means for suppressing an increase in source/drain parasitic resistance, a first side-wall spacer is used as a material with a dielectric constant greater than that of an oxide layer. In addition, an electric field in an N- or P-area of source/drain region at the gate edge is strengthened so as to reduce the resistance of a parasitic resistance under the first side-wall spacer. Thus, an effective result of an increased driving current can be obtained.